Glossary term
Glossary term
Infrastructure and Serving
A programmable linear algebra accelerator with on-chip high bandwidth memory that is optimized for machine learning workloads. Multiple TPU chips are deployed on a TPU device.
Created for this library
An ML platform team specifies TPU chip configurations in its training job templates for predictable performance.
A research engineer monitors TPU chip utilization to spot underused chips and tune batch size accordingly.
An ML platform team selects TPU chip generations for each training job based on workload characteristics and cost.
Definition source: Google for Developers Machine Learning Glossary | Creative Commons Attribution 4.0 License